The present invention relates to a digital decoder and, more particularly, to a decoder for simultaneously effecting two conversion methods to produce a dual sets of outputs. The decoder is implemented on an integrated circuit substrate using MOS FET's (field effect transistors). The decoder operates to convert a binary input of n bits, having a value x, into two decoded outputs, each having a different format. In a first method, output lines Z.sub.1 -Z.sub.m exist, m=2.sup.n, and only output line Z.sub.x+1 is set high while the remainder are set low in response to a binary input having a value x. In a second method, there are (m-1) output lines, Y.sub.1 -Y.sub.(m-1), with Y.sub.1 being the least significant. The second method produces a decoded output wherein x output lines are set high beginning with Y.sub.1 up to Y.sub.x with the remaining lines being set low. For instance, if the value of x is three then Y.sub.1 -Y.sub.3 are set high and if x is 0 then no lines are set high.
Various configurations of decoders exist. A first type of decoder is shown in Japanese laid open Patent Publication (KOKAI) No. SHO 63151223 which discloses a 3 to 8 line decoder as an embodiment. The decoder implements the first method of conversion wherein one output line is set high dependent upon the binary value of the input lines. For example, consider a decoder having three input lines B.sub.1, B.sub.2 and B.sub.3 and eight output lines Z.sub.1 -Z.sub.8. If the binary value of the input on lines B.sub.1 -B.sub.3 is x, then output line Z.sub.x+1 is set high while the remainder are set low.
A second type of decoder implements the second method of conversion wherein there are n input lines B.sub.1, B.sub.2, and B.sub.3, where n is 3, and (2.sup.n -1) output lines. Thus, where n is 3 there are seven output lines Y.sub.1 -Y.sub.7. More generally, there are outputs Y.sub.1 -Y.sub.(m-1), with Y.sub.1 being the least significant and m=2.sup.n. The second method produces a decoded output wherein x output lines are set high, Y.sub.1 -Y.sub.x, and the remainder are set at zero.
The decoders are implemented by logic circuitry specific to the desired functional output. The logic circuitry employs various typical logic gates including inverters, AND gates, OR gates and gates executing other logic functions. Each of the known decoders executes a single function, or conversion method. Situations exist wherein decoded outputs generated by both methods are required. A typical solution to this requirement is to provide two decoders having common inputs, and individual sets of outputs. This approach of using multiple function specific circuits results in increased complexity and an increase in the number of circuit elements.
A conversion decoder is disclosed in Japanese laid open Patent Publication (KOKAI) No. 63156427. The conversion decoder converts output of the first method into output formated according to the second method. Specifically, input in the form Z.sub.1 -Z.sub.8 of the first method is converted into output corresponding to the form of Y.sub.1 -Y.sub.7 of the second method for each value of x. This type of decoder is sometimes referred to as an allotting decoder.
By using the conversion decoder above in conjunction with the first decoder discussed above, both forms of decoded output are obtainable. The outputs of the first decoder are input to the conversion decoder to obtain another set of outputs having the format of the second decoder. While both types of outputs are achieved without incorporating all the circuitry of the second decoder, the resulting serial combination is complex and requires a significant number of circuit elements. Input to output time delays are also increased in accordance with the number of elements. Thus, there exists a need for a dual conversion decoder with fewer circuit elements and reduced complexity.